1. Field of the Invention
The present invention relates to a semiconductor memory device having a serial access mode and, more particularly, to a semiconductor memory device having a higher operation speed in serial access than that in random access.
2. Description of the Related Art
In an access scheme of a random access type semiconductor memory device, data is almost serially read out. In order to increase a serial access speed, a scheme in which a latch circuit for latching storage data of one-line memory cells connected to a selected word line is arranged, and data is serially read out from the latch circuit has been conventionally considered. That is, a sense amplifier/latch circuit is connected to bit lines arranged in a memory cell array. When a word line is selected storage data of one-line memory cells connected to this word line are detected and amplified by the sense amplifier section of the sense amplifier/latch circuit and latched by the latch section. The data latched by the latch section are sequentially and serially read out in response to column addresses of the memory cell array.
By employing the above scheme, a series of operations, i.e., selection of a word line corresponding to each memory cell and amplification of data read out from the memory cells, can be omitted. Therefore, an access time can be decreased to 1/2 or less the random access time. When a column address is caused to correspond to an LSB of an input address and serial access is performed, data can be read out at a higher speed than random access.
However, in the above described scheme, the maximum number of bytes capable of high-speed accessing is limited to the number of latch sections (e.g., X bytes), i.e., the number of bits of a column of a memory cell array. Data cannot always be read from all the X bytes depending on an address randomly accessed first (an accessed address represents a position near a change in row). In addition, when a memory device employing the above scheme is accessed by a CPU, the following system must be arranged. When the device is randomly accessed, a wait command is sent to the CPU and a data fetch period is prolonged from one cycle to two cycles. On the contrary, when the device is serially accessed, data is fetched without the wait command. However, when the scheme is employed, an address of a memory device which receives the wait command is physically determined, thus resulting in a cumbersome operation in the CPU. In order to avoid this, a wait signal is output from the memory device, and data representing random access or serial access is sent to the CPU. However, a large number of memory devices are supported by a CPU, and a logic circuit such as a multiplexer is required to receive the wait signal. Therefore, an advantage of high-speed serial access cannot be sufficiently utilized. The memory device requires an external connection pin for sending the wait signal, and it is far from a standard memory device.